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    • WindowGenerator

    Modified by 2015.06.01

    Design

    WindowGenerator

    Version
    1.0

    Modified
    2015-05-19

    Source

    WindowGenerator

    IP-GUI

    WindowGenerator IP-GUI

    Function

    Generate window.
    The lowest "color_width" bits of "out_data" is the top left corner pixel of the window!
    In pipeline mode, it will give the first output after window_width / 2 + 1 cycles while the input enable.
    In req-ack mode, before the first window can be output, it will give a input ack for every req, then you can give the next input data.

    Files

    Name Function
    WindowGenerator.v Main module
    WindowGenerator_TB.sv Test bench

    Parameters

    Name Type Range Default Description
    work_mode unsigned 0 for Pipline, 1 for Req-ack 0 This module's working mode.
    window_width unsigned 2 - 15 3 The width(and height) of window.
    color_width unsigned 1 - 12 8 Color's bit wide.

    Ports

    Name Port Type Range Default Description
    clk input unsigned None None Clock.
    rst_n input unsigned None None Reset, active low.
    in_enable input unsigned None None Input data enable, in pipeline mode, it works as another rst_n, in req-ack mode, only it is high will in_data can be really changes.
    in_data input unsigned color_width * window_width - 1 : 0 None Input data, it must be synchronous with in_enable.
    out_ready output unsigned None None Output data ready, in both two mode, it will be high while the out_data can be read.
    out_data output unsigned color_width * window_width * window_width - 1 : 0 None Output data, it will be synchronous with out_ready.
    input_ack output unsigned None None Input ack, only used for req-ack mode, this port will give a ack while the input_data received.

    Simulations

    Simulations for this module just support 500xN, Gray-scale and binary images ! And module just supports conf 'width' 3 and 5 !

    Waves

    Pipeline mode

    Pipline mode

    ReqAck mode

    ReqAck mode

    Original

    Original

    Results

    Results
    HDL functional simulation for pipeline mode is on the left, for req-ack mode is on the middle, and which on the right is the soft simulation

    PSNR

    1-3 1-5 2-3 2-5 Total
    OK OK OK OK OK

    Utilization

    Slice LUTs* Slice Registers
    73 74

    Timing

    The max Data Path Delay is 2.325ns, so:

    FMax = 430.10MHz

    Thanks

    The sources of images for simulations:
    パセリ-COMITIA100