Modified by 2015.05.11
Interface in all IPCores in F-I-L include some similar and basal ports, and some extended ports. The basal ports, otherwise, the ports in each module, can support all functions for some modules, but for others they are not enuogh, in that time, the extended ports is needed. Moreover, because of the two different working mode in each module, two interface protocols are needed.
These port are designed as follows:
- clk: Synchronous clock.
- rst_n: Global reset, active low.
- in_enable: Input enable signal, for controlling input data stream.
- in_data: Input data stream, the source for processing.
- out_ready: Output ready signal, a sign of end of processing.
- out_data: Output data stream, the result by processing.
These ports ensured the basal functions of each module:
All modules work as follows:
At first, module must be reseted and initialized, then the in_data will input with the in_enable enable. After many cycles, the out_data can be read, then out_ready will be high.
Because of the uniqueness of every module, basal ports can not meet the demand, so many extended ports are needed, these ports are designed al follows:
- x: Indefinite ports, they depend on the demand of module's function.
- in_count_x: The x component of input coordinate, always used for geometric transformation.
- in_count_y: The y component of input coordinate, always used for geometric transformation.
- out_count_x: The x component of output coordinate, always used for geometric transformation.
- out_count_y: The y component of output coordinate, always used for geometric transformation
- frame_addr: For controlling frame, giving the address with a data.
Combine the basal ports and extended ports are, all demand will be meet:
After defining the hardware of interface, we must define the protocols. Because of every module's two working mode, and compatible with existing interface, for the simplest design, I make the two working mode conforming a same interface.
In pipline mode, if the in_enable is enable, as the out_ready is enable, out_data will follow the change of in_data:
This mode is used for applications which need data stream, because of the buffers of pipline, it can reach the max Fmax in theory.
In the mode, the in_enable is used as "req", and the out_ready is used as "ack", only in the rising edge of in_enable the in_data will be inputed, and after the out_ready enable, the out_data will be held until the next in_enable's changing:
This mode is always used for some special module, like "Histogram", because there is not meanning for these module. Moreover, this mode can be used for interaction between FPGA and software by AXI-Interface.