• F-I-L
  • Wiki
  • Source
  • Contact

    • RowsGenerator

    Modified by 2015.06.01

    Design

    RowsGenerator

    Version
    1.0

    Modified
    2015-05-18

    Source

    RowsGenerator

    IP-GUI

    RowsGenerator IP-GUI

    Function

    Generate rows cache, this module just support Pipeline mode now !!!
    The lowest color_width-bits of out_data are the first row!
    You can configure all fifos by yourself, but fifos in one project whcih have same name must have same configurations.
    And you can just change the "Write Depth" and "Fifo Implementation", the Read Latency must be 1 !
    Give the first output after rows_width * (rows_depth + 1) cycles while the input enable.

    Files

    Name Function
    RowsGenerator.v Main module
    RowsGenerator_TB.sv Test bench
    Fifo1xWidthRows.xci Xilinx IPCore file.
    Fifo1xWidthRows_funcsim.v Model for functional simulation.
    Fifo4xWidthRows.xci Xilinx IPCore file.
    Fifo4xWidthRows_funcsim.v Model for functional simulation.
    Fifo8xWidthRows.xci Xilinx IPCore file.
    Fifo8xWidthRows_funcsim.v Model for functional simulation.
    Fifo12xWidthRows.xci Xilinx IPCore file.
    Fifo12xWidthRows_funcsim.v Model for functional simulation.

    Parameters

    Name Type Range Default Description
    rows_width unsigned 2 - 15 3 The width of rows.
    im_width unsigned 1 - 4096 320 The width of image.
    color_width unsigned 1 - 12 8 Color's bit wide.
    im_width_bits unsigned Depend on width of image 9 The bits of width of image.

    Ports

    Name Port Type Range Default Description
    clk input unsigned None None Clock.
    rst_n input unsigned None None Reset, active low.
    in_enable input unsigned None None Input data enable, it works as fifo0's wr_en.
    in_data input unsigned color_width - 1 : 0 None Input data, it must be synchronous with in_enable.
    out_ready output unsigned None None Output data ready, in both two mode, it will be high while the out_data can be read.
    out_data output unsigned rows_width * color_width - 1 : 0 None Output data, it will be synchronous with out_ready.The lowest color_width-bits of this are the first row!

    Instances

    Name Type Description
    Fifo Fifo1xWidthRows Fifo which has 1 width and N depth (0 < N < 4096), used for rows cache which color_width is 1.You can configure the fifo by yourself, but all fifos in one project whcih have same name must have same configurations.And you can just change the "Write Depth" and "Fifo Implementation", the Read Latency must be 1 !
    Fifo Fifo4xWidthRows Fifo which has 4 width and N depth (0 < N < 4096), used for rows cache which color_width is 2, 3 and 4.You can configure the fifo by yourself, but all fifos in one project whcih have same name must have same configurations.And you can just change the "Write Depth" and "Fifo Implementation", the Read Latency must be 1 !
    Fifo Fifo8xWidthRows Fifo which has 8 width and N depth (0 < N < 4096), used for rows cache which color_width is 5, 6, 7 and 8.You can configure the fifo by yourself, but all fifos in one project whcih have same name must have same configurations.And you can just change the "Write Depth" and "Fifo Implementation", the Read Latency must be 1 !
    Fifo Fifo12xWidthRows Fifo which has 12 width and N depth (0 < N < 4096), used for rows cache which color_width is 9, 10, 11 and 12.You can configure the fifo by yourself, but all fifos in one project whcih have same name must have same configurations.And you can just change the "Write Depth" and "Fifo Implementation", the Read Latency must be 1 !

    Simulations

    Simulations for this module just support 512xN, Gray-scale and binary images ! And module just supports conf 'width' 3 and 5 !

    Waves

    Pipline mode

    Pipline mode

    Original

    Original

    Results

    Results
    HDL functional simulation for pipeline mode is on the left, for req-ack mode is on the middle, and which on the right is the soft simulation

    PSNR

    1-3 1-5 2-3 2-5 Total
    OK OK OK OK OK

    Utilization

    Slice LUTs* Slice Registers
    610 237

    Timing

    The max Data Path Delay is 3.514ns, so:

    FMax = 284.57MHz

    Thanks

    The sources of images for simulations:
    パセリ-絵描き見習い