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    • FrameController

    Modified by 2015.05.14

    Design

    FrameController

    Version
    1.0

    Modified
    2015-05-12

    Source

    FrameController

    IP-GUI

    FrameController IP-GUI

    Function

    For controlling a BlockRAM from xilinx.Give the first output after ram_read_latency cycles while the input enable.

    Files

    Name Function
    FrameController.v Main module
    FrameController_TB.sv Test bench
    BRam8x512x512_funcsim.v Model for functional simulation.

    Parameters

    Name Type Range Default Description
    work_mode unsigned 0 for Pipline, 1 for Req-ack 0 This module's working mode.
    wr_mode unsigned 0 for Write, 1 for Read 0 This module's WR mode.
    color_width unsigned 1 - 12 8 Color's bit width.
    im_width unsigned 1 - 4096 320 Width of image.
    im_height unsigned 1 - 4096 240 Height of image.
    addr_width unsigned Depend on im_width and im_height. 17 Address bit width of a ram for storing this image.
    ram_read_latency unsigned 0 - 15, Depend on your using ram. 2 RL of RAM, in xilinx 7-series device, it is 2.
    row_init unsigned Depend on your input offset. 0 The first row you want to storing, used for eliminating offset.

    Ports

    Name Port Type Range Default Description
    clk input unsigned None None Clock.
    rst_n input unsigned None None Reset, active low.
    in_enable input unsigned None None Input data enable, in pipeline mode, it works as another rst_n, in req-ack mode, only it is high will in_data can be really changes.
    in_data input unsigned color_width - 1 : 0 None Input data, it must be synchronous with in_enable.
    out_ready output unsigned None None Output data ready, in both two mode, it will be high while the out_data can be read.
    out_data output unsigned color_width - 1 : 0 None Output data, it will be synchronous with out_ready.
    ram_addr output unsigned addr_width - 1 : 0 None Address for ram.

    Simulations

    Simulations for this module just support Gray-scale and 512x512 images !

    Waves

    Pipline mode, Write

    Pipline mode, Write

    Pipline mode, Read

    Pipline mode, Read

    ReqAck mode, Write

    ReqAck mode, Write

    ReqAck mode, Read

    ReqAck mode, Read

    Results

    Results
    HDL functional simulation for pipeline mode is on the left, for req-ack mode is on the middle, and which on the right is the soft simulation

    PSNR

    1 2 3 Total
    1000000.00 1000000.00 1000000.00 1000000.00

    Utilization

    Slice LUTs* Slice Registers
    38 17

    Timing

    The max Data Path Delay is 1.921ns, so:

    FMax = 520.56MHz

    Thanks

    The sources of images for simulations:
    月岡月穂-ゆらゆら
    LM7-oxford eleKtricity
    cotta-池