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    • ContrastTransform

    Modified by 2015.05.16

    Design

    ContrastTransform

    Version
    1.0

    Modified
    2015-05-16

    Source

    ContrastTransform

    IP-GUI

    ContrastTransform IP-GUI

    Function

    Change the contrast of an image.Give the first output after mul_delay + 1 cycles while the input enable.

    Files

    Name Function
    ContrastTransform.v Main module
    ContrastTransform_TB.sv Test Bench
    Multiplier12x24CT.xci Xilinx IPCore file.
    Multiplier12x24CT_funcsim.v Model for functional simulation.

    Parameters

    Name Type Range Default Description
    work_mode unsigned 0 for Pipelines, 1 for Req-ack 0 This module's working mode.
    color_channels unsigned None 3 Channels for color, 1 for gray, 3 for rgb, etc.
    color_width unsigned 1 - 12 8 Color's bit wide
    mul_delay unsigned Depend your multilpliers' configurations 3 Delay for multiplier.

    Ports

    Name Port Type Range Default Description
    clk input unsigned None None Clock.
    rst_n input unsigned None None Reset, active low.
    ct_scale input unsigned 23 : 0 None Scale for contrast, fixed, 12bits.12bits.
    in_enable input unsigned None None Input data enable, in pipelines mode, it works as another rst_n, in req-ack mode, only it is high will in_data can be changes.
    in_data input unsigned color_channels * color_width - 1 : 0 None Input data, it must be synchronous with in_enable.
    out_ready output unsigned None None Output data ready, in both two mode, it will be high while the out_data can be read.
    out_data output unsigned color_channels * color_width - 1 : 0 None Output data, it will be synchronous with out_ready.

    Instances

    Name Type Description
    Mul Multiplier12x24CT Multiplier for Unsigned 12bits x Unsigned 24bits, used for fixed multiplication.You can configure the multiplier by yourself, then change the "mul_delay".All Multiplier's pipeline stage must be same, you can not change the ports' configurations!

    Simulations

    Simulations for this module just support RGB and Gray-scale images !

    Waves

    Pipeline mode

    Pipeline mode

    ReqAck mode

    ReqAck mode

    Original

    Original

    Results

    Results
    HDL functional simulation for pipeline mode is on the left, for req-ack mode is on the middle, and which on the right is the soft simulation

    PSNR

    1-0.2 1-3.3 2-0.2 2-3.3 Total
    55.11 61.09 55.09 59.53 57.70

    Utilization

    Slice LUTs* Slice Registers DSP
    38 27 3

    Timing

    The max Data Path Delay is 2.746ns, so:

    FMax = 364.16MHz

    Thanks

    The sources of images for simulations:
    LM7-sn