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    • FrameController2

    Modified by 2015.06.01

    Design

    FrameController2

    Version
    1.0

    Modified
    2015-05-25

    Source

    FrameController2

    IP-GUI

    FrameController2 IP-GUI

    Function

    Controlling a frame(block ram etc.), writing or reading with counts.
    For controlling a BlockRAM from xilinx.
    Give the first output after mul_delay + 2 + ram_read_latency cycles while the input enable.

    Files

    Name Function
    FrameController2.v Main module
    FrameController2_TB.sv Main module
    Multiplier12x12FR2.xci Xilinx IPCore file.
    Multiplier12x12FR2_funcsim.v Model for functional simulation.

    Parameters

    Name Type Range Default Description
    work_mode unsigned 0 for Pipline, 1 for Req-ack 0 This module's working mode.
    wr_mode unsigned 0 for Write, 1 for Read 0 This module's WR mode.
    data_width unsigned None 8 Data bit width.
    im_width unsigned 1 - 4096 320 Width of image.
    im_height unsigned 1 - 4096 240 Height of image.
    im_width_bits unsigned Depend on width of image 9 The bits of width of image.
    addr_width unsigned Depend on im_width and im_height. 17 Address bit width of a ram for storing this image.
    ram_read_latency unsigned 0 - 15, Depend on your using ram. 2 RL of RAM, in xilinx 7-series device, it is 2.
    mul_delay unsigned Depend on your multilpliers' configurations 3 Delay for multiplier.

    Ports

    Name Port Type Range Default Description
    clk input unsigned None None Clock.
    rst_n input unsigned None None Reset, active low.
    in_count_x input unsigned im_width_bits - 1 : 0 None Input pixel count for width.
    in_count_y input unsigned im_width_bits - 1 : 0 None Input pixel count for height.
    in_enable input unsigned None None Input data enable, in pipeline mode, it works as another rst_n, in req-ack mode, only it is high will in_data can be really changes.
    in_data input unsigned data_width - 1 : 0 None Input data, it must be synchronous with in_enable.
    out_ready output unsigned None None Output data ready, in both two mode, it will be high while the out_data can be read.
    out_data output unsigned data_width - 1 : 0 None Output data, it will be synchronous with out_ready.
    ram_addr output unsigned addr_width - 1 : 0 None Address for ram.

    Instances

    Name Type Description
    Mul Multiplier12x12FR2 Multiplier for Unsigned 12bits x Unsigned 12bits, used for creating address for frame.You can configure the multiplier by yourself, then change the "mul_delay".You can not change the ports' configurations!

    Simulations

    Simulations for this module just support Gray-scale images !

    Waves

    Pipline mode, Write

    Pipline mode, Write

    Pipline mode, Write

    Pipline mode, Read

    ReqAck mode, Write

    ReqAck mode, Write

    ReqAck mode, Read

    ReqAck mode, Read

    Results

    Results
    HDL functional simulation for pipeline mode is on the left, for req-ack mode is on the middle, and which on the right is the soft simulation

    PSNR

    1 2 3 Total
    1000000.00 1000000.00 1000000.00 1000000.00

    Utilization

    Slice LUTs* Slice Registers DSP
    38 64 1

    Timing

    The max Data Path Delay is 2.485ns, so:

    FMax = 402.41MHz

    Thanks

    The sources of images for simulations:
    月岡月穂-ゆらゆら
    LM7-oxford eleKtricity
    cotta-池