Shear
Modified by 2015.05.14
Design
Shear
Version
1.0
Modified
2015-05-28
Source
IP-GUI
Function
Shearing an image by your given sh.
Give the first output after 1 cycle while the frame input ready.
Files
| Name | Function |
|---|---|
| Shear.v | Main module |
| Shear_TB.sv | Test bench |
| Multiplier12x25SSHR.xci | Xilinx IPCore file. |
| Multiplier12x25SSHR_funcsim.v | Model for functional simulation. |
| FixedRoundSigned1.v | Source file. |
| BRam8x512x512_funcsim.v | Simulation file. |
| FrameController.v | Simulation file. |
| FrameController2.v | Simulation file. |
| Multiplier12x12FR2_funcsim.v | Simulation file. |
Parameters
| Name | Type | Range | Default | Description |
|---|---|---|---|---|
| work_mode | unsigned | 0 for Pipeline, 1 for Req-ack | 0 | This module's working mode. |
| data_width | unsigned | None | 8 | Data bit width. |
| im_width | unsigned | 1 - 4096 | 320 | Width of image. |
| im_height | unsigned | 1 - 4096 | 240 | Height of image. |
| im_width_bits | unsigned | Depend on width of image | 9 | The bits of width of image. |
| mul_delay | unsigned | Depend on your multilpliers' configurations, 1 - 14 | 3 | Delay for multiplier. |
| ram_RL | unsigned | Depend on your FrameController | 7 | Delay for FrameController. |
Ports
| Name | Port | Type | Range | Default | Description |
|---|---|---|---|---|---|
| clk | input | unsigned | None | None | Clock. |
| rst_n | input | unsigned | None | None | Reset, active low. |
| sh_u | input | signed | Fixed number, 13bits.12bits | None | Sh for horizontal. |
| sh_v | input | signed | Fixed number, 13bits.12bits | None | Sh for vertical. |
| in_enable | input | unsigned | None | None | Input data enable, in pipeline mode, it works as another rst_n, in req-ack mode, only it is high will in_data can be really changes. |
| frame_in_ready | input | unsigned | None | None | Connect to out_ready in FrameController. |
| frame_in_data | input | unsigned | data_width - 1 : 0 | None | Connect to out_data in FrameController. |
| frame_enable | output | unsigned | None | None | Connect to in_enable in FrameController. |
| frame_out_count_x | output | unsigned | im_width_bits - 1 : 0 | None | Connect to in_count_u in FrameController. |
| frame_out_count_y | output | unsigned | im_width_bits - 1 : 0 | None | Connect to in_count_v in FrameController. |
| out_ready | output | unsigned | None | None | Output data ready, in both two mode, it will be high while the out_data can be read. |
| out_data | output | unsigned | data_width - 1 : 0 | None | Output data, it will be synchronous with out_ready. |
Instances
| Name | Type | Description |
|---|---|---|
| MulU | Multiplier12x25SSHR | Multiplier for Unsigned 12bits x Signed 25bits, used for fixed multiplication.You can configure the multiplier by yourself, then change the "mul_delay".All Multiplier's pipeline stage must be same, you can not change the ports' configurations! |
| MulV | Multiplier12x25SSHR | Multiplier for Unsigned 12bits x Signed 25bits, used for fixed multiplication.You can configure the multiplier by yourself, then change the "mul_delay".All Multiplier's pipeline stage must be same, you can not change the ports' configurations! |
| FRSU | FixedRoundSigned1 | For rounding signed fixed number. |
| FRSV | FixedRoundSigned1 | For rounding signed fixed number. |
Simulations
Simulations for this module just support 512x512 and Gray-scale images !
Waves
Pipeline mode
ReqAck mode
Original
Results
Conf for testing:
| ush | vsh |
|---|---|
| 0.5 | 0.5 |
| -1.671 | 0.539 |
| 0.824 | -1.793 |
HDL functional simulation for pipeline mode is on the left, for req-ack mode is on the middle, and which on the right is the soft simulation
PSNR
| 1--1.671x0.539 | 1-0.5x0.5 | 1-0.824x-1.793 | Total |
|---|---|---|---|
| 52.36 | 52.38 | 1000000.00 | 333368.25 |
Utilization
512x512, width of color is 8.
| Slice LUTs* | Slice Registers | DSP |
|---|---|---|
| 212 | 166 | 2 |
Timing
512x512, width of color is 8.
The max Data Path Delay is 4.103ns, so:
FMax = 243.72MHz
Thanks
The sources of images for simulations:
ぜろきち-白の夢