LightnessTransform
Modified by 2015.05.16
Design
LightnessTransform
Version
1.0  
Modified
2015-05-06  
Source
IP-GUI

Function
Change the lightness of an image.Give the first output after 2 cycles while the input enable.
Files
| Name | Function | 
|---|---|
| LightnessTransform.v | Main module | 
| LightnessTransform_TB.sv | Testbench | 
| True2Comp | Convert true code to complemental code. Just used for simulation | 
Parameters
| Name | Type | Range | Default | Description | 
|---|---|---|---|---|
| work_mode | unsigned | 0 for Pipelines, 1 for Req-ack | 0 | This module's working mode. | 
| color_channels | unsigned | 1 - Inf | 3 | Channels for color, 1 for gray, 3 for rgb, etc. | 
| color_width | unsigned | 1 - 12 | 8 | Color's bit wide | 
Ports
| Name | Port | Type | Range | Default | Description | 
|---|---|---|---|---|---|
| clk | input | unsigned | None | None | Clock. | 
| rst_n | input | unsigned | None | None | Reset, active low. | 
| lm_gain | input | signed | color_width : 0 | None | Gain for luminance, signed.The value must be true code if gain is positive, if negative, must be complemental code. | 
| in_enable | input | unsigned | None | None | Input data enable, in pipelines mode, it works as another rst_n, in req-ack mode, only it is high will in_data can be changes. | 
| in_data | input | unsigned | color_channels * color_width - 1 : 0 | None | Input data, it must be synchronous with in_enable. | 
| out_ready | output | unsigned | None | None | Output data ready, in both two mode, it will be high while the out_data can be read. | 
| out_data | output | unsigned | color_channels * color_width - 1 : 0 | None | Output data, it will be synchronous with out_ready. | 
Simulations
Simulations for this module just support RGB and Gray-scale images !
Waves
Pipeline mode

ReqAck mode

Original

Results

HDL functional simulation for pipeline mode is on the left, for req-ack mode is on the middle, and which on the right is the soft simulation
PSNR
| 1--90 | 1-100 | 2--90 | 2-100 | Total | 
|---|---|---|---|---|
| 1000000.00 | 1000000.00 | 1000000.00 | 1000000.00 | 1000000.00 | 
Utilization
| Slice LUTs* | Slice Registers | 
|---|---|
| 67 | 57 | 
Timing
The max Data Path Delay is 2.533, so:
FMax = 394.78MHz
Thanks
The sources of images for simulations:
LM7-NL