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    • Mirror

    Modified by 2015.05.14

    Design

    Mirror

    Version
    1.0

    Modified
    2015-05-26

    Source

    Mirror

    IP-GUI

    Mirror IP-GUI

    Function

    Getting a mirror of your given image.
    Give the first output after 1 cycle while the input enable.

    Files

    Name Function
    Mirror.v Main module
    Mirror_TB.sv Test bench

    Parameters

    Name Type Range Default Description
    work_mode unsigned 0 for Pipeline, 1 for Req-ack 0 This module's working mode.
    data_width unsigned None 8 Data bit width.
    im_width unsigned 1 - 4096 320 Width of image.
    im_height unsigned 1 - 4096 240 Height of image.
    im_width_bits unsigned Depend on width of image 9 The bits of width of image.

    Ports

    Name Port Type Range Default Description
    clk input unsigned None None Clock.
    rst_n input unsigned None None Reset, active low.
    mode input unsigned 00 for horizontal, 01 for vertical, 10 or 11 for all None Mode for mirror.
    in_enable input unsigned None None Input data enable, in pipeline mode, it works as another rst_n, in req-ack mode, only it is high will in_data can be really changes.
    in_data input unsigned data_width - 1 : 0 None Input data, it must be synchronous with in_enable.
    in_count_x input unsigned im_width_bits - 1 : 0 None Input pixel count for width.
    in_count_y input unsigned im_width_bits - 1 : 0 None Input pixel count for height.
    out_ready output unsigned None None Output data ready, in both two mode, it will be high while the out_data can be read.
    out_data output unsigned data_width - 1 : 0 None Output data, it will be synchronous with out_ready.
    out_count_x output unsigned im_width_bits - 1 : 0 None Output pixel count for height.
    out_count_y output unsigned im_width_bits - 1 : 0 None Output pixel count for height.

    Simulations

    Simulations for this module just support Gray-scale images !

    Waves

    Pipeline mode

    Pipeline mode

    ReqAck mode

    ReqAck mode

    Original

    Original

    Results

    Results
    HDL functional simulation for pipeline mode is on the left, for req-ack mode is on the middle, and which on the right is the soft simulation

    PSNR

    1-All 1-Horizontal 1-Vertical 2-All 2-Horizontal 2-Vertical Total
    1000000.00 1000000.00 1000000.00 1000000.00 1000000.00 1000000.00 1000000.00

    Utilization

    512x512, width of color is 8.

    Slice LUTs* Slice Registers
    11 27

    Timing

    512x512, width of color is 8.

    The max Data Path Delay is 1.941ns, so:

    FMax = 515.19MHz

    Thanks

    The sources of images for simulations:
    LM7-nk