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    • Scale

    Modified by 2015.05.14

    Design

    Scale

    Version
    1.0

    Modified
    2015-05-28

    Source

    Scale

    IP-GUI

    Scale IP-GUI

    Function

    Scaling an image by your given scale.
    Give the first output after 1 cycle while the frame input ready.

    Files

    Name Function
    Scale.v Main module
    Scale_TB.sv Test bench
    Multiplier12x24SCL.xci Xilinx IPCore file.
    Multiplier12x24SCL_funcsim.v Model for functional simulation.
    FixedRoundUnsigned.v Source file.
    BRam8x512x512_funcsim.v Simulation file.
    FrameController.v Simulation file.
    FrameController2.v Simulation file.
    Multiplier12x12FR2_funcsim.v Simulation file.

    Parameters

    Name Type Range Default Description
    work_mode unsigned 0 for Pipeline, 1 for Req-ack 0 This module's working mode.
    data_width unsigned None 8 Data bit width.
    im_width unsigned 1 - 4096 320 Width of image.
    im_height unsigned 1 - 4096 240 Height of image.
    im_width_bits unsigned Depend on width of image 9 The bits of width of image.
    mul_delay unsigned Depend on your multilpliers' configurations, 1 - 14 3 Delay for multiplier.
    ram_RL unsigned Depend on your FrameController 7 Delay for FrameController.

    Ports

    Name Port Type Range Default Description
    clk input unsigned None None Clock.
    rst_n input unsigned None None Reset, active low.
    scale_x input unsigned Fixed number, 6bits.18bits None Scale for horizontal, must be reciprocal of real scale.
    scale_y input unsigned Fixed number, 6bits.18bits None Scale for vertical, must be reciprocal of real scale.
    in_enable input unsigned None None Input data enable, in pipeline mode, it works as another rst_n, in req-ack mode, only it is high will in_data can be really changes.
    frame_in_ready input unsigned None None Connect to out_ready in FrameController.
    frame_in_data input unsigned data_width - 1 : 0 None Connect to out_data in FrameController.
    frame_enable output unsigned None None Connect to in_enable in FrameController.
    frame_out_count_x output unsigned im_width_bits - 1 : 0 None Connect to in_count_x in FrameController.
    frame_out_count_y output unsigned im_width_bits - 1 : 0 None Connect to in_count_y in FrameController.
    out_ready output unsigned None None Output data ready, in both two mode, it will be high while the out_data can be read.
    out_data output unsigned data_width - 1 : 0 None Output data, it will be synchronous with out_ready.

    Instances

    Name Type Description
    MulX Multiplier12x24SCL Multiplier for Unsigned 12bits x Unsigned 24bits, used for fixed multiplication.You can configure the multiplier by yourself, then change the "mul_delay".All Multiplier's pipeline stage must be same, you can not change the ports' configurations!
    MulY Multiplier12x24SCL Multiplier for Unsigned 12bits x Unsigned 24bits, used for fixed multiplication.You can configure the multiplier by yourself, then change the "mul_delay".All Multiplier's pipeline stage must be same, you can not change the ports' configurations!
    FRUX FixedRoundUnsigned For rounding fixed number.
    FRUY FixedRoundUnsigned For rounding fixed number.

    Simulations

    Simulations for this module just support 512x512 and Gray-scale images !

    Waves

    Pipeline mode

    Pipeline mode

    ReqAck mode

    ReqAck mode

    Original

    Original

    Results

    Conf for testing:

    xscale yscale
    1.97 0.213
    0.391 2.17
    0.4 0.4

    Results
    HDL functional simulation for pipeline mode is on the left, for req-ack mode is on the middle, and which on the right is the soft simulation

    PSNR

    1-0.391x2.17 1-0.4x0.4 1-1.97x0.213 Total
    1000000.00 1000000.00 1000000.00 1000000.00

    Utilization

    512x512, width of color is 8.

    Slice LUTs* Slice Registers DSP
    77 69 2

    Timing

    512x512, width of color is 8.

    The max Data Path Delay is 3.372ns, so:

    FMax = 296.55MHz

    Thanks

    The sources of images for simulations:
    あきのん-[C84]こもれび